ternlang-hdl vs ternlang-core vs ternlang-ml

Verilog-2001 codegen for balanced ternary — BET processor primitives, sparse matmul array, FPGA simulation wrapper.

Compiler and VM for Ternlang — balanced ternary language with affirm/tend/reject trit semantics, @sparseskip codegen, and BET bytecode execution.

Ternary ML inference kernels — TritFloat (confidence-native ternary float), TritFloatTensor, sparse_matmul (@sparseskip), TritMatrix, deliberation engine, action gate, and MLP for the Ternlang ecosystem.